Semiconductor processing can involve fabrication of various circuit devices over a semiconductor substrate, (such as, for example, a semiconductor wafer substrate) to form integrated circuitry. Semiconductor processing frequently involves formation of thin layers or films, with such layers or films ultimately being incorporated into various integrated circuit features.
Problems can occur during the formation of layers. For instance, it can be desired for layers to be relatively conformal across an undulating topography, and yet it is found that it is very difficult in practice to form a conformal layer across a complex topography using coating type methods. Such problem is illustrated in FIG. 1 which shows a semiconductor construction 10 formed in accordance with prior art processing.
Construction 10 includes a semiconductor substrate 12. Substrate 12 can comprise, consist essentially of, or consist of, for example, monocrystalline silicon lightly-doped with background p-type dopant. To aid in interpretation of this disclosure and the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
An electrically insulative material 14 is over substrate 12, and is patterned so that a pair of openings 16 and 18 extend through the insulative material to an upper surface of substrate 12. Opening 16 is shown to have a higher critical dimension than opening 18, or in other words is shown to have a higher ratio of height to width than opening 18.
The insulative material 14 has uppermost surfaces 15 proximate the openings 16 and 18, and has sidewall surfaces 17 forming sidewall peripheries of the openings. Substrate 12 has an upper surface 13 which forms bottom peripheries of the openings 16 and 18. The surfaces 13, 15 and 17 together define an undulating topography. A layer 20 is shown formed across such undulating topography. Layer 20 is intended to be formed conformally across the undulating topography, and a dashed line 21 diagrammatically illustrates where an upper surface of layer 20 would be if the layer were formed conformally across the undulating topography of surfaces 13, 15 and 17. However, instead of being formed conformally across the undulating topography of surfaces 13, 17 and 15, the layer 20 builds up in various locations so that the layer ends up with the upper surface 23 rather than the desired upper surface 21. More specifically, layer 20 fills the narrow opening 16, rather than forming conformally along the sidewalls 17 of such narrow opening; and forms rounded corners 25 within the wide opening 18, rather than forming the more square corners 27 associate with the idealized upper surface 21 that would result if layer 20 formed conformally within wide opening 18.
It would be desirable to develop methods for forming layers conformally over undulating topographies associate with semiconductor constructions, and to incorporate such conformal layers into integrated circuitry. Although the invention was motivated, at least in part, by a desire to form conformal layers during semiconductor processing, it is to be understood that the invention can have additional applications.
Another aspect of the prior art is that depositions have been conducted utilizing aluminum-containing materials provided over titanium-oxide-containing materials to promote adhesion to wafers having substantially non-undulating (i.e., flat or planar) surface topographies.